One of the advancements of modern technology is the decision-driven control loop (“DDCL”), in which input symbols are fed to a detector and the detector produces an output based on the input symbols. The DDCL includes a feedback loop, wherein the input symbols (prior to being fed to the detector) and the detector's output are evaluated against each other. The result of this evaluation is generally referred to as a decision, and it is this decision that is then used to drive the control loop.
DDCLs are useful in many communication devices requiring a high degree of precision and/or flexibility of decision. For instance, in a circuit for a read channel used for magnetic recording, a DDCL is useful, e.g., for adjusting gain, timing, adaptive finite impulse response (FIR), and/or baseline levels.
Selection of memory path length for a data detector (such as a Viterbi detector) used in a DDCL has an effect on DDCL performance. The data detector tends to be more accurate if a longer memory path is used to derive the detector's output. The longer the memory path, however, the greater the delay, or latency, between the input symbols and the detector output. Accordingly, problems arise in the conflict between the competing needs of accuracy and speed.